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Silicon Bug Files

A bingeable field guide to the bug classes that cause respins — and the verification that catches each one.

Featured · Co-founder, ChipGPT

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The series

7 cases · read them in order, or jump to a bug class.

  1. 01

    Right proof for each bug

    method · the field guide

    Why one verification method can't catch every bug class.

  2. 02

    The bug your simulator can't see

    critical · escapes to silicon

    A clock-domain bug that is invisible to simulation by construction.

  3. 03

    Spec-to-RTL drift

    critical · ~70% of respins

    The RTL drifts one bit from the spec and every test still passes.

  4. 04

    One missing +1

    critical · silent failure

    A missing increment turns a hardware AES engine into a fixed-keystream cipher.

  5. 05

    A bus that hangs forever

    critical · liveness

    Three masters wait on each other in a circle and the bus never recovers.

  6. 06

    The counter that never gives up

    high · infinite retry

    An 8-bit retry counter compared to a 16-bit limit it can never reach.

  7. 07

    Counted twice

    medium · timing

    An I2C controller that adds the bus fall time twice.

See it live

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